Current solutions exist for integrating electronic and photonic devices on a single substrate—i.e., making photonic integrated circuits on silicon. By bonding a wafer of III-V material as an active region to silicon and removing the substrate, lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic devices with integrated circuits; however, there only limited solutions for coupling between hybrid and silicon-only waveguides exist.
FIGS. 1A-1C are diagrams of prior art hybrid III-V/silicon optical devices. Optical device 100 of FIG. 1A and FIG. 1B includes buried oxide (BOX) layer 102 and silicon semiconductor layer 104, which together form a silicon-on-insulator (SOI) structure. Prior art device 100 further includes air gaps 106 for providing lateral optical mode confinement.
III-V layers 108 and 110 form the active regions of device 100, and, along with electrical contacts 112, are bonded to the above described SOI structure to form lasers, amplifiers, modulators, and other hybrid optical devices.
Prior art device 100 uses an evanescent coupling approach between its hybrid and silicon only waveguides. In this approach the III-V waveguide dimensions are reduced (i.e., tapered, as shown in the top view of device 100 in FIG. 1A) and the optical mode power is maintained in the silicon waveguide (i.e., the fundamental mode is transformed into a mode where the majority of the mode power is in the silicon waveguide). The III-V material is then truncated at tip 120.
There are several issues with prior art device 100. First, air gaps 106 create mechanical instability for the device. Second, efficiency of device 100 comes from tip 120—the narrower the tip, the less scattering loss will occur, and the more optically efficient the device is. Current state of the art III-V semiconductor processing (i.e., lithography) is limited, thus it is difficult to make tip 120 small, and thereby difficult to make device 100 efficient. This constraint causes a tradeoff between the confinement of the optical mode in the untapered region and the scattering loss at the tip.
FIG. 1C is a diagram of a prior art hybrid III-V/silicon device. Prior art optical device 150 includes BOX regions 152, silicon layer 154, including ridge 156, spacer layer 158, quantum well region 160 and III-V layer 162. In this device, because III-V layer 162 does not participate in lateral confinement, there will always be structures required in silicon layer 154—i.e., via ridge 156, for lateral waveguiding. This structure limits the lower refractive index that can be achieved.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.